Teklatech Raise $1.5 Million In Funding

Newly developed clock-timing technology for computer chips will change production costs, scalability, and design reliability significantly

Newly developed clock-timing technology for computer chips will change production costs, scalability, and design reliability significantly. The technology is estimated to retrieve global market impact in the chip industry within the next two years.

“I don’t believe in hierarchical, top-down leadership when it comes to innovative enterprises. When I ask talented engineers to join this entrepreneurial voyage, they need to be able to see financial benefits, professional recognition, as well as freedom to operate. If you want skilled people to take a chance, they need to be provoked, challenged, and empowered,” says Tobias Bjerregaard, founder and CEO of Teklatech.

Recognizing the need to address increasing on-chip variability at early chip design stages, Teklatech has developed an innovative approach to top-level clock distribution. The technology makes it possible to implement ultimately scalable, globally synchronous systems. It enables a modular approach to system-level clock distribution and timing validation, which complements SoC design approaches used in the industry today.

“Teklatech’s clock grid technology is potentially a giant leap for scalability and cost reduction in chip design. The patents are in the pipeline, the technology well-documented and highly innovative. With this funding, Teklatech will be able to attract pioneering engineers, evaluate field applications further, and launch new visions for market standards,”says Jens Ove Albertsen, Investment Manager, SEED Capital Denmark.

The funding is needed mainly to recruit R&D engineers to further develop the company’s Clock Assembly and Timing (CAT) tool, as well as to recruit field application engineers to promote the tool and support industry evaluation of the technology. Eventually, the funding will mature Teklatech for international Series A funding.

“Not only large-scale, nanometer SoC designs benefit from the technology,” says Tobias Bjerregaard. “Our approach inherently leads to clock spreading. We believe this to have positive effects on IR drop, supply bounce, EMI, and on-chip noise, and we are currently in the process of quantizing these effects.”

The methods applied are variability-robust and technology agnostic, and thus track well into sub-100 nanometer geometries. The CAT tool enables a predictable path to complete SoC integration, reducing design time and the risk of costly chip re-spins.

Teklatech was founded in 2006, as a spin-off from the Technical University of Denmark (DTU).

Main investors are Ulrik Danneskiold-Samsoe Holding and founding investor, SEED Capital Denmark.

Teklatech will take part in the exhibition forum of this year’s Design Automation Conference (DAC) in San Diego, June 4-7.

Original story